/**************************************************************************** 
* 
* Copyright (c) 2023  C*Core -   All Rights Reserved  
* 
* THIS SOFTWARE IS DISTRIBUTED "AS IS," AND ALL WARRANTIES ARE DISCLAIMED, 
* INCLUDING MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* 
* PROJECT     : CCFC2011BC           
* DESCRIPTION : CCFC2011BC siul low level drivers common code 
* HISTORY     : Initial version.
* @file     siul_lld.c
* @version  1.1
* @date     2023 - 02 - 20
* @brief    Initial version.
*
*****************************************************************************/
#include "CCFC2011BC.h"
#include "siul_lld.h"

/************************************************************************
 *    MCU ID Register #1 (MIDR1), MCU ID Register #2 (MIDR2)
 ************************************************************************/
/* @brief SIUL  MCU ID Register #1, MCU Part Number(lower 16 bits) read.
 * @return refer: MIDR1_PartNum_Type
 * */
uint16_t SIUL_MIDR1_PartNumRead(void)
{
    return SIU.MIDR1.B.PARTNUM;
}

/* @brief SIUL  MCU ID Register #1, Package Settings read.
 * @return refer: MIDR1_PKG_Type
 * */
uint8_t SIUL_MIDR1_PackSetRead(void)
{
    return SIU.MIDR1.B.PKG;
}

/* @brief SIUL  MCU ID Register #1, Major Mask Revision read.
 * @return Major Mask Revision
 * */
uint8_t SIUL_MIDR1_MajorMaskRead(void)
{
    return SIU.MIDR1.B.MAJOR_MASK;
}

/* @brief SIUL  MCU ID Register #1, Minor Mask Revision read.
 * @return Minor Mask Revision
 * */
uint8_t SIUL_MIDR1_MinorMaskRead(void)
{
    return SIU.MIDR1.B.MINOR_MASK;
}

/* @brief SIUL  MCU ID Register #2, Manufacturer read.
 * @return refer: MIDR2_SF_Manufacturer_Type
 * */
uint8_t SIUL_MIDR2_MakerRead(void)
{
    return SIU.MIDR2.B.SF;
}

/* @brief SIUL  MCU ID Register #2, Flash memory 1 size read.
 * @return refer: MIDR2_FlashSize1_Type
 * */
uint8_t SIUL_MIDR2_FlashSize1Read(void)
{
    return SIU.MIDR2.B.FLASH_SIZE_1;
}

/* @brief SIUL  MCU ID Register #2, Flash memory 2 size read.
 * @return refer: MIDR2_FlashSize2_Sel_Type
 * */
uint8_t SIUL_MIDR2_FlashSize2SelRead(void)
{
    return SIU.MIDR2.B.FLASH_SIZE_2;
}

/* @brief SIUL  MCU ID Register #2, MCU Part Number(upper 8 bits) read.
 * @return refer: MIDR2_PartNum_Type
 * */
uint8_t SIUL_MIDR2_PartNumRead(void)
{
    return SIU.MIDR2.B.PARTNUM;
}

/* @brief SIUL  MCU ID Register #2, Data Flash present read.
 * @return refer: MIDR2_DataFlash_Type
 * */
uint8_t SIUL_MIDR2_DataFlashRead(void)
{
    return SIU.MIDR2.B.EE;
}
/************************************************************************
 *    Interrupt Status Flag Register (ISR)
 ************************************************************************/
/* @brief ISR, Clear External Interrupt Status Flag x.
 * @param eifNum: ISR_EIF_Type
 * */
void SIUL_EXTI_Clear_Flag(uint32_t eifNum)
{
    SIU.ISR.R = eifNum;
}

/* @brief ISR, Read External Interrupt Status Flag x.
 * @return refer: ISR_EIF_Type
 * */
uint32_t SIUL_EXTI_Get_Flag(void)
{
    return SIU.ISR.R;
}
/************************************************************************
 *     Interrupt Request Enable Register (IRER)
 ************************************************************************/
/* @brief IRER, External Interrupt Request Enable x.
 * @param ireNum: IRER_IRE_Type
 * */
void SIUL_EXT_IntReqEnable(uint32_t ireNum)
{
    SIU.IRER.R |= ireNum;
}
/************************************************************************
 *     Interrupt Rising-Edge Event Enable Register (IREER)
 ************************************************************************/
/* @brief IREER, Enable rising-edge events.
 * @param ireeNum: IREER_IREE_Type
 * */
void SIUL_IntRisingEventEnable(uint32_t ireeNum)
{
    SIU.IREER.R |= ireeNum;
}

/************************************************************************
 *     Interrupt Falling-Edge Event Enable Register (IFEER)
 ************************************************************************/
/* @brief IFEER, Enable falling-edge events.
 * @param ifeeNum: IFEER_IFEE_Type
 * */
void SIUL_IntFallingEventEnable(uint32_t ifeeNum)
{
    SIU.IFEER.R |= ifeeNum;
}

/************************************************************************
 *     Interrupt Filter Enable Register (IFER)
 ************************************************************************/
/* @brief IFER, Enable digital glitch filter on the interrupt pad input.
 * @param ifeNum: IFER_IFE_Type
 * */
void SIUL_IntFilterEnable(uint32_t ifeNum)
{
    SIU.IFER.R |= ifeNum;
}
/************************************************************************
 *    Pad Configuration Registers (PCR0-PCR148)
 ************************************************************************/
/* @brief SIUL PCR Init.
 * @param pcr_num: PCR_Pin_Type, 0~148 (Spec: Functional port pins)
 *        padType: SIUL_PCR_Type
 * */
void SIUL_Init(uint8_t pcrNum, uint16_t padType)
{
    SIU.PCR[pcrNum].R = padType;
}

/* @brief SIUL PCR Init for GPIO.
 * @param pcr_num: PCR_Pin_Type, 0~148 (Spec: Functional port pins)
 * */
void SIUL_Init_GPIO_Out(uint8_t pcrNum, uint16_t mode)
{
    SIU.PCR[pcrNum].R = mode;
}

/* @brief SIUL PCR Init for EIRQ.
 * @param pcr_num: PCR_Pin_Type, 0~148 (Spec: Functional port pins)
 * */
void SIUL_Init_EIRQ(uint8_t pcrNum)
{
    SIU.PCR[pcrNum].R = PCR_EIRQ;
}

/* @brief SIUL PCR Init for ADC.
 * @param pcr_num: PCR_Pin_Type, 0~148 (Spec: Functional port pins)
 * */
void SIUL_Init_ADC(uint8_t pcrNum)
{
    SIU.PCR[pcrNum].R = PCR_ADC;
}

/************************************************************************
 *     Pad Selection for Multiplexed Inputs Registers (PSMI0_3-PSMI60_63)
 ************************************************************************/
/* @brief PSMI, Pad Selection Bits
 *        Each PADSEL field selects the pad currently used for a certain
 *          input function.
 * @param selNum: SIUL_PSMI_Num_Type
 *        mapNum: SIUL_PSMI_Mapping_Type
 * */
void SIUL_PadSelMuxInput(uint8_t selNum, uint8_t mapNum)
{
    SIU.PSMI[selNum].B.PADSEL = mapNum;
}

/************************************************************************
 *     GPIO Pad Data Output Registers (GPDO0_3-GPDO148_151)
 ************************************************************************/
/* @brief SIUL, GPIO Output Status Write.
 * @param pcr_num: 0~151 (Spec: Functional port pins).
 *        status:  high = 1, low = 0.
 * */
void SIUL_GPIO_OutputWrite(uint8_t pcrNum, uint8_t status)
{
    SIU.GPDO[pcrNum].B.PDO = status;
}

/************************************************************************
 *     GPIO Pad Data Input Registers (GPDI0_3-GPDI148_151)
 ************************************************************************/
/* @brief SIUL, GPIO Input Status Read.
 * @param pcr_num: 0~151 (Spec: Functional port pins).
 * @return high = 1, low = 0.
 * */
uint8_t SIUL_GPIO_InputRead(uint8_t pcrNum)
{
    return SIU.GPDI[pcrNum].B.PDI;
}
/************************************************************************
 *     Parallel GPIO Pad Data Out Registers (PGPDO0-PGPDO4)
 ************************************************************************/
/* @brief SIUL, Parallel port registers for input (PGPDI) and 
 *          output (PGPDO) are provided to allow a complete port 
 *          to be written or read in one operation, dependent on 
 *          the individual pad configuration.
 * @param portNum: SIUL_PGPD_OI_Port_Type.
 *        pinNum: SIUL_PGPD_OI_0_Type, SIUL_PGPD_OI_1_Type,
 *                SIUL_PGPD_OI_2_Type, SIUL_PGPD_OI_3_Type,
 *                SIUL_PGPD_OI_4_Type
 * */
void SIUL_ParallelGPIOPadData_Out(uint8_t portNum, uint32_t pinNum)
{
     SIU.PGPDO[portNum].R = pinNum;
}
/* @brief SIUL, Parallel port registers for input (PGPDI) and 
 *          output (PGPDO) are provided to allow a complete port 
 *          to be written or read in one operation, dependent on 
 *          the individual pad configuration.
 * @param portNum: SIUL_PGPD_OI_Port_Type.
 * @return SIUL_PGPD_OI_0_Type, SIUL_PGPD_OI_1_Type,
 *         SIUL_PGPD_OI_2_Type, SIUL_PGPD_OI_3_Type,
 *         SIUL_PGPD_OI_4_Type
 * */
uint32_t SIUL_ParallelGPIOPadData_In(uint8_t portNum)
{
    return SIU.PGPDI[portNum].R;
}

/************************************************************************
 *     Masked Parallel GPIO Pad Data Out Register (MPGPDO0-MPGPDO9)
 ************************************************************************/
/* @brief SIUL, GPIO Output Status Write.
 * @note  The MPGPDOx registers may only be accessed with 32-bit writes.
 *          8-bit or 16-bit writes will not modify any bits in the register
 *          and will cause a transfer error response by the module. 
 *          Read accesses return '0'.
 * @param portNum: SIUL_MPGPDO_Port_Type
 *        maskPinNum: (must 32-bit write)  SIUL_MPGPDO0_MaskData_Type,
 *                   SIUL_MPGPDO1_MaskData_Type, SIUL_MPGPDO2_MaskData_Type,
 *                   SIUL_MPGPDO3_MaskData_Type, SIUL_MPGPDO4_MaskData_Type,
 *                   SIUL_MPGPDO5_MaskData_Type, SIUL_MPGPDO6_MaskData_Type,
 *                   SIUL_MPGPDO7_MaskData_Type, SIUL_MPGPDO8_MaskData_Type,
 *                   SIUL_MPGPDO9_MaskData_Type
 * */
void SIUL_MaskedParallelGPIOPadData_Out(uint8_t portNum, uint32_t maskPinNum)
{
    SIU.MPGPDO[portNum].R = maskPinNum;
}

/************************************************************************
 *     Interrupt Filter Maximum Counter Registers (IFMC0-IFMC23)
 ************************************************************************/
/* @brief SIUL, Maximum Interrupt Filter Counter setting.
 *          Filter Period = T(CK)*MAXCNTx + n*T(CK)
 *          Where (n can be -1 to 3)
 *          T(CK): Prescaled Filter Clock Period, 
 *                  which is FIRC clock prescaled to IFCP value
 *          T(FIRC): Basic Filter Clock Period: 62.5 ns (fFIRC = 16 MHz)
 * @param cntNum: 0~23.
 *        maxcntNum: 0~15
 * */
void SIUL_IntFilterMacCounter_Set(uint8_t regNum, uint8_t maxcntNum)
{
    SIU.IFMC[regNum].B.MAXCNT = maxcntNum;
}

/************************************************************************
 *     Interrupt Filter Clock Prescaler Register (IFCPR)
 ************************************************************************/
/* @brief SIUL, Interrupt Filter Clock Prescaler setting.
 *          Prescaled Filter Clock Period = T(FIRC) x (IFCP + 1)
 *          T(FIRC) is the fast internal RC oscillator period.
 * @param ifcpNum: 0~15.
 * */
void SIUL_IntFilterClkPres_Set(uint8_t ifcpNum)
{
    SIU.IFCPR.B.IFCP = ifcpNum;
}
